As part of quality control process before shipment, electrical performance of electronic components and integrated circuits arranged on electronic chips are required to be tested before or after these electronic chips are packaged. In light of the current trend towards decreasing the size and enhancing the precision of an electronic package according to market demand, the electronic package has now become smaller in size and with greater circuit density, and is even required to meet a specification of wafer level chip scale packages, where a smallest spacing between two adjacent ones of the electronic components arranged on the electronic chip scale packages is limited to be not greater than 0.5 mm. Hence, research and development of test devices that are suitable for testing these wafer level chip scale packages are also required to meet the current trend.
Referring to FIG. 1, a conventional test device 1 includes a metallic test seat 11 that is formed with a plurality of probe holes 111, and a plurality of spring probes 12 that are respectively received in the probe holes 111. The spring probes 12 are used for being electrically connected to electronic component 100 to be tested. The metallic nature of the test seat 11 produces an electromagnetic shielding effect which prevents the spring probes 12 from electrically interfering with each other. Therefore, the test performance of the test device 1 is enhanced.
However, for firmly positioning the spring probes 12 in the probe holes 111, each probe hole 111 has an internal diameter varied along an axial direction of the probe hole 111, which imposes a limitation when it is desired to decrease a distance between two adjacent ones of the spring probes 12. Hence, the conventional test device 1 cannot be used to test the electrical performance of the wafer level chip scale packages.
Further referring to FIG. 2, each of the spring probes 12 of the conventional test device 1 is surrounded by more than one insulating rings 19 when installed in a respective one of the probe holes 111. Arrangement of the insulating rings 19 increases difficulty in using the conventional test device 1 to test the wafer level chip scale packages. Therefore, there is still a need in the art to provide a test device suitable for wafer level chip scale packages.